module top_tb;

reg clk;
reg rstn;
//reg rx_dv;
//reg  [7:0] rxd;
//wire [7:0] txd;
//wire tx_en;
// use interface

my_if input_if(clk, rstn);
my_if output_if(clk, rstn);

dut U_DUT(
     .clk  (clk            )
    ,.rstn (rstn           )
    ,.rxd  (input_if.data  )
    ,.rx_dv(input_if.valid )
    ,.txd  (output_if.data ) 
    ,.tx_en(output_if.valid)
);

initial begin: test_top
    //my_driver drv;
    //drv = new("drv", null);
    //drv.main_phase(null);
    // UVM factory
    run_test();
    //$finish;
end

initial begin
    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);
    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);
    uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);
end

initial begin
    clk = 0;
    forever begin
        #100;
        clk = ~clk;
    end
end

initial begin
    rstn = 1'b0;
    #1000;
    rstn = 1'b1;
end

initial begin
    //$fsdbDumpfile("");
    $fsdbDumpvars();
end
endmodule
